1. Field of the Invention
The present invention relates to a capacitor of a memory device and a fabrication method thereof. More particularly, the present invention relates to a capacitor of a memory device having a vertical metal electrode/metal oxide electrode and a method of fabricating the same.
2. Description of the Related Art
A ferroelectric random access memory (FRAM) is a nonvolatile memory device that may be used in computers, MP3 players, digital cameras, personal digital assistants (PDAs), and other electronic devices. The capacitance of a ferroelectric capacitor per unit area should be increased in order to provide a highly-integrated ferroelectric memory device, which includes one transistor and one capacitor.
For a given dielectric material, a capacitor's area may be increased in order to increase its capacitance C, as given by Equation (1) below.
                    C        =                  ɛ          ⁢                      A            t                                              (        1        )            where ε is the permittivity, A is the effective area and t is the thickness of a dielectric material.
The capacitance can be increased by reducing the thickness and increasing the effective area of the dielectric layer. However, when using a planar capacitor structure, increasing the capacitor's area limits integration of a semiconductor device. Thus, there is an inherent trade off between increasing integration and increasing capacitance. For example, if the space for the capacitor is reduced to increase integration, the planar area of the capacitor is also reduced, decreasing its capacitance. Therefore, there is a continuing effort to develop a three-dimensional capacitor structure that both increases capacitance and improves integration of a device having the capacitor.
There are two basic structures of a three-dimensional ferroelectric capacitor, a trench type and a stack type. The trench type uses a lower metal electrode formed in a recess on a transistor structure, with a ferroelectric thin film deposited on the lower metal electrode. The stack type uses a ferroelectric thin film deposited on a lower metal electrode protruding from a transistor structure. These two types of three-dimensional ferroelectric capacitors will be explained with reference to FIGS. 1A and 1B, which illustrate cross-sectional views of a trench type and a stack type three-dimensional ferroelectric capacitor, respectively.
FIG. 1A illustrates a trench type ferroelectric capacitor, in which a third insulating layer 3, e.g. silicon dioxide (SiO2) is deposited on a second insulating layer 2, and the third insulating layer 3 is etched, thereby forming a concave opening 5. A ruthenium (Ru) or Ru oxide layer 6 is formed on the concave opening 5 and, using chemical mechanical polishing (CMP), the upper surface of the third insulating layer 3 is exposed. Thus, the Ru or the Ru oxide layer 6 remains only inside the concave opening 5. Then, a ferroelectric thin film 7 and an upper electrode 8 are sequentially deposited, thereby forming a three-dimensional ferroelectric capacitor. The capacitor also includes a first insulating layer 1, a Ru plug 4, and a polysilicon plug 9 for connecting the capacitor to a semiconductor device.
The ferroelectric capacitor has a structure of lower electrode/ferroelectric material/upper electrode. The lower electrode in particular should use a metal oxide electrode in order to maintain the good fatigue characteristics of the ferroelectric capacitor. However, a metal oxide electrode normally used for the ferroelectric capacitor, e.g., iridium dioxide (IrO2), or ruthenium dioxide (RuO2), breaks down in a high-temperature vacuum atmosphere typically required during the ferroelectric thin film deposition. Thus, if a ferroelectric thin film is deposited on the metal oxide electrode, the metal oxide electrode may react with the ferroelectric thin film, deteriorating its ferroelectric properties. Therefore, the lower electrode of the ferroelectric capacitor should be formed such that a metal electrode covers the metal oxide electrode.
As a result, a thickness of the lower electrode increases. When the lower electrode 6 having an increased thickness is deposited on the narrow diameter trench or concave opening 5, the aspect ratio of the remaining opening rapidly increases. Thus, stable step coverage is difficult to achieve during the formation of the ferroelectric thin film. When depositing a typical ferroelectric material such as lead zirconate titanate (PZT) or barium strontium titanate (BST) on a lower electrode in the opening having a high aspect ratio using chemical vapor deposition (CVD), it is almost impossible to achieve step coverage at temperatures higher than about 500° C.
FIG. 1B illustrates a cross-sectional view of a stack type three-dimensional capacitor structure. A Ru plug 11 is formed inside a dielectric layer 12, and is connected to a lower electrode 14. A ferroelectric layer 15 and an upper electrode 16 are sequentially formed on the lower electrode 14.
The stack type capacitor structure of FIG. 1B is more easily formed than the trench type capacitor structure shown in FIG. 1A, because the ferroelectric layer is not affected by step coverage in accordance with the thickness of the lower metal electrode. However, the stack type capacitor structure, which is fabricated by forming a lower electrode and etching the lower electrode as shown in FIG. 1B, also has many problems in its actual manufacturing process, as explained in detail below.
First, since a chemically stable precious metal is normally used for the lower electrode 14, e.g., Ir, platinum (Pt), or Ru, it is almost impossible to etch the lower electrode in a vertical direction. Thus, in practice, the etching is normally performed at an angle of about 70°. However, this increases the area of the capacitor, since the lower surface becomes greater than the upper surface. As a result, the unit cell area of a memory device also increases, thereby decreasing integration.
Second, production is expensive. Since the area of the three-dimensional capacitor structure is primarily increased by the area of the lateral sides of the lower electrode 14, the lower electrode 14 should be as thick as possible in the stack type capacitor. However, considering the cost of the precious metal used in the lower electrode 14, such a thick lower electrode 14 is not desirable. Additionally, the time for deposition and etching of the lower electrode 14 is lengthened, further increasing the production cost.
Third, the stack type capacitor formed by etching may not improve fatigue characteristics of the metal oxide electrode. When an electric field is applied to the upper electrode and the lower electrode, a polarization phenomenon of the ferroelectric layer is generated in vertical portions of the upper and lower electrodes and in a vertical direction. Oxygen atoms move in the metal oxide electrode along the direction perpendicular to the electric field, thereby improving fatigue characteristics. In order to realize the stack type capacitor by etching, if a lower metal layer is coated on the metal oxide electrode and etched, the ferroelectric layer formed on the lower electrode may show good fatigue characteristics, since the metal oxide electrode is perpendicular to the electric field. However, the metal oxide electrode on the lateral side of the lower electrode is not perpendicular to the electric field, thereby deteriorating fatigue characteristics.